1. Technical Field
The invention relates to a decoding method, and more particularly, to a decoding method, a memory storage device, a memory controlling circuit unit and a decoding circuit for a low density parity code.
2. Description of Related Art
The markets of digital cameras, cellular phones, and MP3 players have expanded rapidly in recent years, resulting in escalated demand for storage media by consumers. The characteristics of data non-volatility, low power consumption, and compact size make the rewritable non-volatile memory module (e.g., flash memory) ideal for being built in the portable multi-media devices as cited above.
Generally, some error correcting codes are usually added to data stored in the rewritable non-volatile memory module. The error correcting codes in conventional art usually adopts an algebraic decoding algorithm such as BCH code, in which a correcting capability is limited. At present days, a probabilistic decoding algorithm under development such as a low density parity code (LDPC) is gradually mature to include a more preferable correcting capability. However, when a decoding is performed by using the low density parity code, an entire codeword needs to be entered, and a result from the decoding is going to be the entire codeword accordingly. In some implementations, inputting and outputting the entire codeword may increase a decoding latency to expand demands for bandwidth of a buffer memory. Therefore, how to decrease the decoding latency for the low density parity code is one of the major subjects for person skilled in the art.
Nothing herein should be construed as an admission of knowledge in the prior art of any portion of the present invention. Furthermore, citation or identification of any document in this application is not an admission that such document is available as prior art to the present invention, or that any reference forms a part of the common general knowledge in the art.